Verification is a tedious task that may occupy a considerable amount of time of programmers. Specifically, a lot of time may be invested in locating faults (typically referred to as “bugs”) in the program. Automatic fault localization techniques were introduced that are aimed at addressing this problem. For example, automatic fault localization may involve the use of coverage information.
When testing a code, the extent to which that code was actually tested—typically referred to as “coverage”—may be measured.
There are various kinds of coverage metrics, like code coverage, functional coverage, etc.
In the process of verification of an electronic design, when grading coverage for that design, a refinement file may be generated that includes entities in the design which a user may wish to exclude from the calculation of coverage grading.
To-date, when a verified electronic design is incorporated in a larger design, a new refinement file may be needed for the verification process of the larger design, which may typically be produced typically be manually editing the refinement file that was associated with the previously verified design.